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74ALVC245 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
September 2001 Revised March 2005
74ALVC245 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
General Description
The ALVC245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The T/R input determines the direction of data flow. The OE input disables both the A and B ports by placing them in a high impedance state. The 74ALVC245 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O compatibility up to 3.6V. The 74ALVC245 is fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation.
Features
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s Power-off high impedance inputs and outputs s Supports Live Insertion and Withdrawal (Note 1) s tPD
3.4 ns max for 3.0V to 3.6V VCC 3.9 ns max for 2.3V to 2.7V VCC 6 ns max for 1.65V to 1.95V VCC
s Uses patented Quiet Series noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance:
Human body model ! 2000V Machine model ! 200V
Note 1: To ensure the high impedance state during power up and power down, OEn should be tied to VCC through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:
Order Number 74ALVC245WM 74ALVC245MTC 74ALVC245MTCX_NL (Note 2) Package Number M20B MTC20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code. Note 2: "_NL" indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Logic Symbol
Pin Descriptions
Pin Names OE T/R A0-A7 B0-B7 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
Quiet Series is a trademark of Fairchild Semiconductor Corporation.
(c) 2005 Fairchild Semiconductor Corporation
DS500647
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74ALVC245
Connection Diagram
Truth Table
Inputs OE L L H T/R L H X Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH Z State on A0-A7, B0-B7 (Note 3) Outputs
H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Note 3: Unused bus terminals during HIGH Z State must be held HIGH or LOW.
Logic Diagram
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74ALVC245
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) (Note 5) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 6)
Power Supply Operating Input Voltage (VI) Output Voltage (VO) Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V 10 ns/V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed, limited to 4.6V. Note 6: Floating or unused control inputs must be held HIGH or LOW.
1.65V to 3.6V 0V to VCC 0V to VCC
40qC to 85qC
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VIL LOW Level Input Voltage 1.65 - 1.95 2.3 - 2.7 2.7 - 3.6 VOH HIGH Level Output Voltage IOH IOH IOH IOH Min 0.65 x VCC 1.7 2.0 0.35 x VCC 0.7 0.8 VCC - 0.2 1.2 2.0 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 V V V V Max Units
100 PA 4 mA 6 mA 12 mA
1.65 - 3.6 1.65 2.3 2.3 2.7 3.0
IOH VOL LOW Level Output Voltage IOL IOL IOL IOL IOL II IOZ ICC Input Leakage Current 3-STATE Output Leakage Quiescent Supply Current Increase in ICC per Input
24 mA
100 PA 4 mA 6 mA 12 mA 24 mA
3.0 1.65 - 3.6 1.65 2.3 2.3 2.7 3.0 3.6 3.6 0 3.6 3 - 3.6
0 d VI d 3.6V 0 d VO d 3.6V VI VIH V CC or GND, IO VCC 0.6V
r5.0 r10
10 750
PA PA PA PA
'ICC
3
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74ALVC245
AC Electrical Characteristics
TA Symbol Parameter VCC Min tPHL, tPLH tPZL, tPZH tPLZ, tPHZ Propagation Delay Output Enable Time Output Disable Time 1.3 1.6 1.7 CL 3.3V r 0.3V Max 3.4 5.5 5.5 50 pF VCC Min 2.7V Max 3.9 6.3 5.3 VCC Min 1.0 2.0 0.8
40qC to 85qC, RL
500: CL 2.5V r 0.2V Max 3.5 6.0 4.8 30 pF VCC Min 1.5 2.7 1.5 1.8V r 0.15V Max 6.0 8.6 8.0 ns ns ns Units
Capacitance
Symbol CIN CI/O CPD Input Capacitance Input/ Output Capacitance Power Dissipation Capacitance Parameter Control A or B Ports VI VI Conditions 0V or VCC 0V or VCC 10 MHz, CL 0 pF TA VCC 3.3 3.3 3.3 2.5 1.8 Outputs Disabled f 10 MHz, CL 0 pF 3.3 2.5 1.8
25qC
Typical 3 6 30 27 25 0 0 0
Units
pF
Outputs Enabled f
pF
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74ALVC245
AC Loading and Waveforms
TABLE 1. Values for Figure 1 TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ SWITCH Open VL GND
FIGURE 1. AC Test Circuit TABLE 2. Variable Matrix (Input Characteristics: f 1MHz; tr tf 2ns; Z0 Symbol Vmi Vmo VX VY VL VCC 3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V 6V 2.7V 1.5V 1.5V VOL 0.3V VOH 0.3V 6V 2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V VCC*2 1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VOH 0.15V VCC*2 50:)
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
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74ALVC245
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74ALVC245 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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